This invention relates to data processing/control systems wherein a multiplicity of input/output subsystems or channel sources request central processor activity by means of interrupts and where the priority of some data is higher than others necessitating that the multiplexer provide service on prioritized bases.
The priority selecting apparatus is inserted in the input/output lines of a remote multiplexer terminal assembly capable of receiving data from external equipment, processing that data according to a software program, and transmitting data to external equipment. The assembly is capable of operating in a stand-alone configuration at the highest processing level, or it can be used at an intermediate level relying on a host computer for overall system control. The assembly will accept downloaded programs from a host computer as well as execute a stored program. The stored program is usually executed asynchronously; that is, the program executes independently of the host computer.
Many multiplexers have been designed since the introduction of microprocessors. Some of these receive and transmit channel data on a first-in-first-out basis. Others give priority to certain classes of data. U.S. Pat. No. 4,271,467 to Holtey describes one such input/output priority resolver. The apparatus includes a read only memory which establishes the order of priority. The read only memory is responsive to interrupt signals from the input/output devices in order to select the highest priority device requesting service.
U.S. Pat. No. 4,380,065 to Hirtle, et al describes a variable priority communication multiplexer which employs a polling method that prevents any one channel from "hogging" the system. A first-in-first-out (FIFO) memory is used to store the receive and transmit channel numbers of the input and output devices coupled to the multiplexer. An input or output device requesting service responds to its channel number identifier stored in the FIFO memory. The remaining channel numbers in the FIFO are recirculated to give the receive channels priority over the transmit channels. Highest priority is given to the receive channel most recently used and beyond that, equal priority to all transmit channels.
The microprocessor based multiplexer system will typically have input/output devices which request service from a central processing unit by means of interrupts. An interrupt signal will inform the central processing unit that the input/output device either has information to deliver or is in need of an output from the system. Most of the multiplexer systems will have a multiplicity of input/output devices connected in parallel. Conflicts will therefore occur when two or more of the input/output devices simultaneously request service. Since servicing some of the devices are more critical than others there is a need to structure priority into the system. That is, if a higher priority device interrupts the central processing unit at the same time as a lower priority device, the higher priority device must be serviced first. The purpose of this invention is to reduce the circuitry required to implement the interrupt and priority service requirements. We accomplish this by multiplexing the interrupt priority signals across existing address signal lines. As a result, our circuitry is appreciably simplified over the prior art approaches.